The present invention relates to a semiconductor device, such as a very large scale integrated circuit (VLSI), which has a plurality of metal wiring layers, and its manufacturing method.
Recent advanced semiconductor devices, such as VLSI and the like, employ a multi-layer metal wiring structure consisting of a plurality of layers of metal wiring, as a result of progress of large-scale integration technologies.
One example of such a conventional semiconductor device is a three-layer wiring structure semiconductor device whose structure and manufacturing method will be explained below with reference to FIG. 9.
FIG. 9 shows a cross-sectional view of the conventional three-layer wiring structure semiconductor device comprising a silicon substrate 1 provided with a diffusion region, a gate electrode, a polycide electrode, a salicide electrode and a separating electrode, a BPSG film 21 performing as an insulating film formed on the silicon substrate 1, and a first-layer metal wiring 41B formed on the BPSG film 21. A second-layer metal wiring 42B is formed on a first inter-layer insulating film 22, which is formed on the first-layer metal wiring 41B. A third-layer metal wiring 43B is formed on a second inter-layer insulating film 23, which is formed on the second-layer metal wiring 42B. Such a three-layer metal wiring structure, as shown in FIG. 9, allows a total of 10 kinds of connecting patterns among the first- to third-layer metal wirings and the silicon substrate. In the drawing, A represents a connecting pattern conducting the substrate 1 and the first-layer metal wiring 41B, B represents a connecting pattern conducting the first-layer metal wiring 41B and the second-layer metal wiring 42B, C represents a connecting pattern conducting the second-layer metal wiring 42B and the third-layer metal wiring 43B, D represents a connecting pattern conducting the substrate 1 and the first- and second-layer metal wirings 41B, 42B, E represents a connecting pattern conducting the substrate 1 and the first-, second- and third-layer metal wirings 41B, 42B, 43B, F represents a connecting pattern conducting the substrate 1 and the second-layer metal wiring 42B, G represents a connecting pattern conducting the substrate 1 and the second- and third-layer metal wiring 42B, 43B, H represents a connecting pattern conducting the first-layer metal wiring 41B and the third-layer metal wiring 43B, I represents a connecting pattern conducting the substrate 1 and the first- and third-layer wirings 41B, 43B, and J represents a connecting pattern conducting the substrate 1 and the third-layer metal wiring 43B.
Of the 10 connecting patterns above-explained, five of A to E are generally used in practical semiconductor devices.
Hereinafter, conventional three-layer wiring structure semiconductor devices and their manufacturing methods will be explained with reference to FIGS. 10(a)-10(i) and 11(a)-11(i).
FIGS. 10(a)-10(i) show a first conventional semiconductor device and its manufacturing method, wherein the first conventional semiconductor device comprises the above-described five, A to E, connecting patterns.
First, as illustrated in FIG. 10(a), the BPSG film 21, performing as an insulating film, is deposited on the semiconductor substrate 1 which is provided with a transistor region and others. After that, thermal treatment is applied on the BPSG film 21 to planarize the surface of the BPSG film 21 by softening glass. Then, using photolithography technology, a desired-shaped resist pattern 31 is formed on the BPSG film 21.
Next, as illustrated in FIG. 10(b), etching is applied on the BPSG film 21 using a mask of the resist pattern 31, thus forming a contact portion at a predetermined position on the BPSG film 21. Thereafter, the resist pattern 31 is removed and the surface of the BPSG film 21 is cleaned. Then, a first-layer metal film 41A, being composed of titanium film, titanium nitriding film and aluminum alloy film, is formed by sputtering on the BPSG film 21. Subsequently, using photolithography technology, a resist pattern 32 is formed on the first-layer metal film 41A for forming a desired wiring pattern.
Next, as illustrated in FIG. 10(c), etching is applied on the first-layer metal film 41A using a mask of the resist pattern 32, thus forming a first-layer metal wiring 41B. The resist pattern 32 is then removed and the surface of the first-layer metal wiring 41B is cleaned.
Subsequently, as illustrated in FIG. 10(d), a first inter-layer insulating film 22 having a plane surface is formed on the first-layer metal wiring 41B. A resist pattern 33, providing a through hole connecting the first-layer metal wiring 41B and a second-layer metal wiring 42B, is formed on the first inter-layer insulating film 22.
Next, as illustrated in FIG. 10(e), etching is applied on the first inter-layer insulating film 22 using a mask of the resist pattern 33, thereby forming the through hole connecting the first-layer metal wiring 41B and the second-layer metal wiring 42B. The resist pattern 33 is then removed and the first inter-layer insulating film 22 is cleaned. Then, a second-layer metal film 42A, being composed of titanium film, titanium nitriding film and aluminum alloy film, is formed by sputtering on the first inter-layer insulating film 22. Subsequently, using photolithography technology, a resist pattern 34 is formed on the second-layer metal film 42A for forming a desired wiring pattern.
Next, as illustrated in FIG. 10(f), etching is applied on the second-layer metal film 42A using a mask of the resist pattern 34, thus forming a second-layer metal wiring 42B. The resist pattern 34 is then removed and the surface of the second-layer metal wiring 42B is cleaned.
Subsequently, as illustrated in FIG. 10(g), a second inter-layer insulating film 23 having a plane surface is formed on the second-layer metal wiring 42B. A resist pattern 35, providing a through hole connecting the second-layer metal wiring 42B and a third-layer metal wiring 43B, is formed on the second inter-layer insulating film 23.
Next, as illustrated in FIG. 10(h), etching is applied on the second inter-layer insulating film 23 using a mask of the resist pattern 35, thereby forming the through hole connecting the second-layer metal wiring 42B and the third-layer metal wiring 43B. The resist pattern 35 is then removed and the second inter-layer insulating film 23 is cleaned. Then, a third-layer metal film 43A, being composed of titanium film, titanium nitriding film and aluminum alloy film, is formed by sputtering on the second inter-layer insulating film 23. Subsequently, using photolithography technology, a resist pattern 36 is formed on the third-layer metal film 43A for forming a desired wiring pattern.
Finally, as illustrated in FIG. 10(i), etching is applied on the third-layer metal film 43A using a mask of the resist pattern 36, thus forming the third-layer metal wiring 43B. The resist pattern 36 is then removed and the third-layer metal wiring 43B is cleaned. In this manner, the three-layer metal wiring structure is completed.
FIGS. 11(a)-11(i) show a second conventional semiconductor device and its manufacturing method. The multi-layer metal wiring structure of this conventional second semiconductor device is preferably used for large-scale integration of semiconductor device. Formation of metal wiring using only sputtering as shown in FIGS. 10(a)-10(i) tends to encounter with a problem of causing open circuit when a contact or a through hole is small and deep since wiring metal may fail to enter into such a thin and deep through hole. To prevent this kind of electric disconnection, the second conventional semiconductor device forms contacts 41a, 42a and 43a containing tungsten (W) by the chemical vapor deposition (abbreviated as CVD) method after forming the contact or through hole. This is because the CVD method has better applicability for coating of stepped portions. Therefore, a space of the contact or through hole is surely filled with tungsten (W). In FIGS. 11(a)-11(i), the same parts as those of FIGS. 10(a)-10(i) are denoted by identical reference numbers, and will be no more explained.
According to this second conventional semiconductor device, contact and through holes are formed on the connecting region of the substrate or the lower-layer metal wiring, and these contact and through holes are filled with metal material or tungsten W, constituting the upper-layer metal wiring.
However, the above-described first conventional semiconductor device requires a total of 24 steps in the formation of multi-layer metal wiring structure, while the second conventional semiconductor device requires a total of 27 steps in the formation of multi-layer metal wiring structure. The percentage of these steps for formation of multi-layer metal wiring structure is therefore very large in an overall manufacturing process of an LSI. An increase of one metal wiring layer is accompanied by an increase of 7 to 8 manufacturing steps. Utilization of complicated and expensive machines, such as inter-layer insulating film forming machines, sputtering machines, CVD devices for tungsten, directly results in the increase of manufacturing cost.
To reduce the number of steps for manufacturing the multi-layer metal wiring structure, Japanese Patent No. HEI 569308/1993 discloses the method of mutually connecting a substrate, a lower-layer metal wiring, an intermediate-layer metal wiring and an upper-layer metal wiring by providing a ring-shaped connecting portion on the upper-layer metal wiring, forming a through hole extending normally from the central hole of the connecting portion to the substrate, and filling the through hole with metal material to form a contact.
According to the method disclosed in Japanese Patent No. HEI 5-69308/1993, the number of steps of manufacturing a multi-layer metal wiring is reduced. However, the outer diameter of the ring-shaped connecting portion becomes large. It means that the ring-shaped connecting portion requires a large area, which encounters with positional restrictions in providing the connecting portion.
Especially, when the upper-layer metal wiring is directly connected to the substrate or the lower-layer metal wiring without connecting to the intermediate-layer metal wiring, the through hole needs to pass through the central hole formed on the connecting portion of the intermediate-layer metal wiring so as not to be brought into contact with the connecting portion. Consequently, the connecting portion of the intermediate-layer metal wiring is so enlarged that it encounters with severe positional restrictions in provision.